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tmp91cu10 91cu10-1 low-voltage cmos 16-bit microcontrollers TMP91CU10F 1. outline and device characteristics the tmp91cu10 is an original toshiba tlcs-900/l1 series 16-bit microcontroller. the tmp91cu10 integrates a 16-bit cpu, rom, ram, multi-functional timer and event counter, general-purpose serial interface, an a/d converter and various other units in a single chip, and has been developed for controlling medium- to large-scale equipment. the tmp91cu10 is housed in a 100-pin mini flat package. the device characteristics are as follows: (1) original high-speed 16-bit cpu (900/h cpu) tlcs-90/900 instruction mnemonics (upwards compatible) 16-mbyte linear address space general-purpose registers and register bank system 16-bit multiplication/division and bit transfer/arithmetic instructions high-speed m dma: 4 channels (1.18 m s at 13.5 mhz) (1.0 m s at 16 mhz) (2) minimum instruction execution time 400 ns at 10 mhz (v cc = 2.0 v) for mask rom products only 296 ns at 13.5 mhz (vcc = 3.0 v) (3) internal ram: 3 kbytes internal rom: 96 kbytes (4) external memory expansion can be expanded up to 16 mbytes (for both programs and data). am8/ 16 pin (selects the external data bus width) can mix 8- and 16-bit external data buses (dynamic bus sizing) . (5) chip select and wait controller: 3 blocks (6) 8-bit timer: 8 channels including event count function: 2 channels (7) 16-bit timer and event counter: 2 channels (8) general-purpose serial interface: 3 channels uart and synchronous modes (9) (10-bit a/d converter: 8 channels for a discussion of how the reliability of microcontrollers can be predicted, please refer to section 1.3 of the chapter entit led quality and reliability assurance / handling precautions. toshiba is continually working to improve the quality and the reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the re sponsibility of the buyer, when utilizing toshiba products, to observe standards of safety, and to avoid situations in which a malfunction o r failure of a toshiba product could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent products specifications. also, please keep in mind the precautions and conditions set forth in the toshiba semiconductor reliability handbook. the products described in this document are subject to the foreign exchange and foreign trade laws. the information contained herein is presented only as a guide for the applications of our products. no responsibility is assum ed by toshiba corporation for any infringements of intellectual property or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any intellectual property or other rights of toshiba corporation or others. 980910ebp1
tmp91cu10 91cu10-2 (10) watchdog timer (11) interrupt functions 2 cpu interrupts (swi instruction and illegal instruction) 26 internal interrupts 7-level priority can be set. 10 external interrupts 7-level priority can be set. (12) i/o ports: 80 pins (13) standby function: 4 halt modes (run, idle2, idle1, stop) (14) clock gear function clock gear: high-frequency clock can be changed from fc to fc/16. dual clock operation (15) low operating voltage 2.0 to 3.6 v (16) package compact 14 mm 14 mm 1.4 mm (0.5 mm pitch)
tmp91cu10 91cu10-3 sclk0/ cts0 ( p92 ) sclk1 (p95) sclk2/ cts2 (p62) an0 to an7 (p50 to p57) av cc av ss v refl v refh txd0 (p90) rxd0 (p91) txd1 (p93) rxd1 (p94) txd2 (p60) rxd2 (p61) ti0/int1 (p70) to1 (p71) to3/int2 (p72) ti4/int3 (p73) to5 (p74) to7/int4 (p75) toa/tob (p86) tib/int8 (p85) tia/int7 (p84) dv ss [3] dv cc [3] x2 xt1 (p96) xt2 (p97) clk ale ea reset rd (p30) wr ( p31 ) hwr ( p32 ) busrq ( p34 ) busak ( p35 ) r/ w ( p36 ) am8/ 16 p37 (p00 to p07) ad0 to ad7 (p10 to p17) ad8/a8 to ad15/a15 (p20 to p27) a0/a16 to a7/a23 pa0 to pa7 p63, p65 to p67 cs0 ( p40 ) cs1 ( p41 ) cs2 ( p42 ) wait (p33) nmi ti8/int5 (p80) into (p64) ti9/int6 (p81) to8 (p82) to9 (p83) 10-bit 8-ch a/d converter serial i/o (ch.0) 8-bit timer (timer 0) serial i/o (ch.2) 8-bit timer (timer 1) 8-bit timer (timer 2) 8-bit timer (timer 3) 8-bit timer (timer 4) 8-bit timer (timer 5) 8-bit timer (timer 6) 8-bit timer (timer 7) serial i/o (ch.1) 16-bit timer (timer 9) port 0 port 1 port 2 port a port 6 cs/wait controller (3-block) interrupt controller 16-bit timer (timer 8) sr 32 bits xwa w a b c d e h l ix iy iz sp xbc xde xhl xix xiy xsp f pc cpu (tlcs-900/h) osc1 clock gear osc2 watchdog timer 3 kb ram 96 kb ram x1 ( ): default function after reset figure 1.1 TMP91CU10F block diagram
tmp91cu10 91cu10-4 2. pin assignment and functions the assignment of input and output pins for the tmp91cu10, their names and functions are described as follows: 2.1 pin assignment figure 2.1.1 shows the pin assignment of the tmp91cu10. 88 p65 p66 89 87 p64/int0 p67 90 86 p63 dvss 91 85 p62/sclk2/cts2 p50/an0 92 84 p61/rxd2 p51/an1 93 83 p60/txd2 p52/an2 94 82 p42/cs2 p53/an3 95 81 p41/cs1 p54/an4 96 80 p40/cs0 p55/an5 97 79 p37 p56/an6 98 78 p36/r/w p57/an7 99 77 p35/busak vrefh 100 76 p34/busrq vrefl 1 75 p33/wait avss 2 74 p32/hwr avcc 3 73 p31/wr p70/ti0/int1 4 72 p30/rd p71/to1 5 71 p27/a7/a23 p72/to3/int2 6 70 p26/a6/a22 p73/ti4/int3 7 69 p25/a5/a21 p74/to5 8 68 p24/a4/a20 p75/to7/int4 9 67 p23/a3/a19 p80/ti8/int5 10 66 p22/a2/a18 p81/ti9/int6 11 65 p21/a1/a17 p82/to8 12 64 p20/a0/a16 p83/to9 13 63 dvcc p84/tia/int7 14 62 dvss p85/tib/int8 15 61 nmi p86/toa/tob 16 60 p17/ad15/a15 p90/txd0 17 59 p16/ad14/a14 p91/rxd0 18 58 p15/ad13/a13 p92/sclk0/cts0 19 57 p14/ad12/a12 p93/txd1 20 56 p13/ad11/a11 p94/rxd1 21 55 p12/ad10/a10 p95/sclk1 22 54 p11/ad9/a9 am8/16 23 53 p10/ad8/a8 clk 24 52 p07/ad7 dvcc 25 51 p06/ad6 dvss 26 50 p05/ad5 x1 27 49 p04/ad4 x2 28 48 p03/ad3 ea 29 47 p02/ad2 reset 30 46 p01/ad1 p96/xt1 31 45 p00/ad0 p97/xt2 32 44 dvcc test1 33 43 ale test2 34 42 pa7 pa0 35 41 pa6 pa1 36 40 pa5 pa2 37 39 pa4 38 pa3 figure 2.1.1 pin assignment diagram
tmp91cu10 91cu10-5 2.2 pin names and functions the names of the input/output pins and their functions are described in table 2.2.1. table 2.2.1 pin names and functions (1/3) pin name number of pins i/o functions p00 to p07 ad0 to ad7 8 i/o i/o port 0: i/o port that allows i/o to be selected at the bit level address (lower): bits 0 to 7 for address and data bus p10 to p17 ad8 to ad15 a8 to a15 8 i/o i/o output port 1: i/o port that allows i/o to be selected at the bit level address and data (upper): bits 8 to 15 for address and data bus address: bits 8 to 15 for address bus p20 to p27 a0 to a7 a16 to a23 8 i/o output output port 2: i/o port that allows i/o to be selected at the bit level (with pull-up resistor) address: bits 0 to 7 for address bus address: bits 16 to 23 for address bus p30 rd 1 output output port 30: output port read: strobe signal for reading external memory when p3 = 0 and p3fc = 1, rd is output and internal memory is read. p31 wr 1 output output port 31: output port write: strobe signal for writing data on pins d0 to 7 p32 hwr 1 i/o output port 32: i/o port (with pull-up resistor) high write: strobe signal for writing data to pins d8 to d15 p33 wait 1 i/o input port 33: i/o port (with pull-up resistor) wait: pin used to request cpu bus wait p34 busrq 1 i/o input port 34: i/o port (with pull-up resistor) bus request: signal used to request high impedance on pins d0 to d15, a0 to a23, rd , wr , hwr , cs0 , cs1 and cs2 . p35 busak 1 i/o output port 35: i/o port (with pull-up resistor) bus acknowledge: signal used to acknowledge high impedance on pins d0 to d15, a0 to a23, rd , wr , hwr , cs0 , cs1 and cs2 by receiving busrq . p36 r/ w 1 i/o output port 36: i/o port (with pull-up resistor) read/write: 1 represents read or dummy cycle; 0 represents write cycle. p37 1 i/o port 37: i/o port p40 cs0 1 i/o output port 40: i/o port (with pull-up resistor) chip select 0: outputs 0 when address is within specified address area. p41 cs1 1 i/o output port 41: i/o port (with pull-up resistor) chip select 1: outputs 0 when address is within specified address area. p42 cs2 1 i/o output port 42: i/o port (with pull-down resistor) chip select 2: outputs 0 when address is within specified address area. p50 to p57 an0 to an7 8 input input port 5: input port analog input: pin used to input to ad converter p60 txd2 1 i/o output port 60: i/o port serial send data 2 (programmable open drain) p61 rxd2 1 i/o input port 61: i/o port serial receive data 2 (programmable open drain) p62 sclk2 cts2 1 i/o i/o input port 62: i/o port serial clock i/o 2 serial data send enable 2 (clear to send) (programmable open drain) p63 1 i/o port 63: i/o port p64 int0 1 i/o input port 64: i/o port interrupt request pin 0: interrupt request pin with programmable level/rising edge p65 to p67 3 i/o port 65 to 67: i/o ports note: a dmac controllers internal memory or i/o devices cannot be accessed using busrq and busak .
tmp91cu10 91cu10-6 table 2.2.1 pin names and function (2/3) pin name number of pins i/o functions p70 ti0 int1 1 i/o input input port 70: i/o port timer input 0: timer 0 input pin interrupt request pin 1: interrupt request on rising edge p71 to1 1 i/o output port 71: i/o port timer output 1: timer 0 or 1 output p72 to3 int2 1 i/o output input port 72: i/o port timer output 3: timer 2 or 3 output interrupt request pin 2: interrupt request on rising edge p73 ti4 int3 1 i/o input input port 74: i/o port timer input 4: timer 4 input interrupt request pin 3: interrupt request on rising edge p74 to5 1 i/o output port 75: i/o port timer output 5: timer 4 or 5 output p75 to7 int4 1 i/o output input port 76: i/o port timer output 7: timer 6 or 7 output interrupt request pin 4: interrupt request on rising edge p80 ti8 int5 1 i/o input input port 80: i/o port timer input 8: timer 8 count or capture trigger signal input interrupt request pin 5: interrupt request pin with programmable rising / falling edge p81 ti9 int6 1 i/o input input port 81: i/o port timer input 9: timer 8 count or capture trigger signal input interrupt request pin 6: interrupt request on rising edge p82 to8 1 i/o output port 82: i/o port timer output 8: timer 8 output pin p83 to9 1 i/o output port 83: i/o port timer output 9: timer 9 output pin p84 tia int7 1 i/o input input port 84: i/o port timer input a: timer 9 count or capture trigger signal input interrupt request pin 7: interrupt request pin with programmable rising / falling edge p85 tib int8 1 i/o input input port 85: i/o port timer input b: timer 9 count or capture trigger signal input interrupt request pin 8: interrupt request on rising edge p86 toa tob 1 i/o output output port 86: i/o port timer output a: timer a output pin timer output b: timer b output pin p90 txd0 1 i/o output port 90: i/o port serial send data 0 (programmable open drain) p91 rxd0 1 i/o input port 91: i/o port serial receive data 0 p92 sclk0 cts0 1 i/o i/o input port 92: i/o port serial clock i/o 0 serial data send enable 0 (clear to send) p93 txd1 1 i/o output port 93: i/o port serial send data 1 (programmable open drain) p94 rxd1 1 i/o input port 94: i/o port serial receive data 1 p95 sclk1 1 i/o i/o port 95: i/o port serial clock i/o 1 p96 xt1 1 i/o input port 96: i/o port (open drain output) low-frequency oscillator connecting pin p97 xt2 1 i/o output port 97: i/o port (open drain output) low-frequency oscillator connecting pin
tmp91cu10 91cu10-7 table 2.2.1 pin names and function (3/3) pin name number of pins i/o functions pa0 to pa7 3 i/o port a0 to a7: i/o ports ale 1 output address latch enable (can be disabled for reducing noise.) nmi 1 input non-maskable interrupt request pin: interrupt request pin with programmable falling edge or both edges. clk 1 output clock output: outputs (external input clock/4) clock. pulled-up during reset ea 1 input the vcc pin should be connected. am8/ 16 1 input address mode: selects external data bus width. the vcc pin should be connected. the data bus width for external access is set by the chip select/wait control register and the port 1 control register. test1/test2 2 output /input test1 should be connected with test2 pin. reset 1 input reset: initializes lsi. (with pull-up resistor) vrefh 1 input reference power supply input pin for ad converter (h) vrefl 1 input reference power supply input pin for ad converter (l) avcc 1 power supply pin for ad converter avss 1 gnd power supply pin for ad converter (0 v) x1/x2 2 i/o oscillator connecting pin test1/test2 2 output /input test1 should be connected with test2 pin. dvcc1 3 power supply pin dvss 3 gnd pin (0 v) note: all pins that have built-in pull-up / pull-down resistors (other than the reset pin) can be disconnected from their built-in pull-up / pull-down resistors by software.
tmp91cu10 91cu10-8 3. operation this section describes the functions and basic operations of the tmp91cu10. please also refer to section 7, precautions, which describes some points requiring careful attention. 3.1 cpu tmp91cu10 device has a built-in high-performance 16-bit cpu (tlcs-900/l1 cpu). (for a basic description of the cpu operation, see the information on the tlcs-900/l1 cpu). this section describes some cpu functions unique to the tmp91cu10 that are not described in the description of the tlcs-900/l1 cpu. 3.1.1 reset figure 3.1.1 shows the basic timing chart for a reset operation. to reset a tmp91cu10 device, the reset pin must be kept at 0 for at least ten consecutive system clock cycles (equivalent to 160 states: 24 m s at 13.5 mhz). the pin must be kept within the specified operating voltage range and stable clock oscillation must be maintained. when a reset signal is received, the cpu is set as follows: the program counter (pc) is set according to the reset vector that is stored from ffff00h to ffff02h. pc (7 to 0) ? data in location ffff00h pc (15 to 8) ? data in location ffff01h pc (23 to 16) ? data in location ffff02h the stack pointer (xsp) for system mode is set to 100h. the bits of the status register sr are set to 111. (the mask register is set to interrupt level 7.) the bit of sr is set to 1 (maximum mode). (note: this device does not support minimum mode. do not set to 0.) the bits of sr are set to 000. (the register banks are cleared to 0.) when the reset is released, instruction execution starts from pc (the reset vector). the reset makes no changes to the values in any cpu internal registers other than those specifically mentioned above. when a reset is received, signal and data processing for built-in i/os, ports and other pins is affected as follows: initializes built-in i/o registers as described in the specifications. sets port pins (including pins also used as built-in i/os) to general-purpose input/output port mode. pulls up the clk pin to 1. sets the ale pin to high impedance (hi-z). note 1: resetting makes no change to the contents of any registed in the cpu except the program counter (pc), status register (sr) and stack pointer (xsp), nor to the data in the internal ram. note 2: the clk pin is pulled up during a reset. when the voltage is externally reduced, there is a possibility of malfunction.
tmp91cu10 91cu10-10 3.2 memory map the tmp91cu10 uses an address area of 128 bytes as the internal i/o area, which is allocated from addresses 000000h to 00007fh. the cpu can access this internal i/o using a short internal code in direct addressing mode. figure 3.2.1 shows the memory map and the accessible area for each cpu addressing mode. ( =internal area) m mcu mode direct area (n) internal i/o (128 bytes) 000000h internal ram (3 kbytes) 000080h 000100h external memory vector table (256 bytes) ffffffh internal rom (96 kbytes) ffff00h 000c80h 010000h fe8000h 64 kbytes area (nn) 16-mbyte area (r) (-r) (r+) (r-r8/16) (r+d8/16) (nnn) note: the stack pointer xsp is set to 100h after a reset. figure 3.2.1 tmp91cu10 memory map
tmp91cu10 91cu10-182 4. electrical characteristics 4.1 absolute maximum ratings parameter symbol rating unit power supply voltage vcc - 0.5 to 4.0 v input voltage vin - 0.5 to vcc + 0.5 v output current (total) s iol 120 ma output current (total) s ioh - 80 ma power dissipation (ta=85 c) pd 600 mw soldering temperature (10 s) tsolder 260 c storage temperature tstg C65 to 150 c operating temperature topr - 40 to 85 c note: the absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. any one of the ratings must not be exceeded. if any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. thus, when designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded. 4.2 dc characteristics (1/2) parameter symbol condition min typ. (note1) max unit fc = 4 to 16 mhz fs = 30 to 34 khz (ta = - 40 to 85 c) 2.7 power supply voltage avcc=vcc avss=vss=0v vcc fc = 4 to 10 mhz fs = 30 to 34 khz (ta = - 40 to 85 c) 2.2 (note 2) 3.6 v vcc 3 2.7 v 0.8 ad0 to 15 vil vcc < 2.7 v 0.4 port2 to a(exceptp87, p5) vil1 0.3 vcc reset , nimi , int0 vil2 0.25 vcc ea , am8/ 16 vil3 0.3 input low voltag x1, port5 vil4 vcc = 2.7 to 3.6 v - 0.3 0.2 vcc vcc 3 2.7 v 2.2 ad0 to 15 vih vcc < 2.7 v 2.0 port2 to a(exceptp87) vih1 0.7 vcc reset , nimi , int0 vih2 0.75 vcc ea , am8/ 16 vih3 vcc - 0.3 input high voltage x1 vih4 vcc = 2.7 to 3.6 v 0.8 vcc vcc+0.3 v note 1: typical values are for ta = 25 c and vcc = 5 v unless otherwise noted. note 2: the operation of the a/d converter is guaranteed at vcc = 2.7 to 3.6 v. x used in an expression shows a frequency for the clock f fph selected by syscr1. the value of x changes according to whether a clock gear or a low speed oscillator is selected. an example value is calculated for fc, with gear=1/fc (syscr1=0000).
tmp91cu10 91cu10-183 4.2 dc characteristics (2/2) parameter symbol condition min typ. (note1) max unit output low voltage vol iol = 1.6 ma (vcc = 2.7 to 3.6 v) 0.45 voh1 ioh = - 400 m a (vcc = 2.2 v 10%) 1.4 output high voltage voh2 ioh = - 400 m a (vcc = 3 v 10 %) 2.4 v darlington drive current (8 output pins max.) idar (note2) vext = 1.5 v rext = 1.1 k w (vcc = 3 v 10%) - 1.0 - 3.5 ma input leakage current ili 0.0 vin vcc 0.02 5 output leakage current ilo 0.2 vin vcc - 0.2 0.05 10 m a power down voltage (@stop,ram back up) vstop vil2 = 0.2 vcc, vih2 = 0.8 vcc 2.0 6.0 v vcc = 3 v 10% 50 250 reset pull up resister rrst vcc = 2.2 v 10% 80 500 k w pin capacitance cio fc = 1 mhz 10 pf schmitt width reset , nimi , int0 vth 0.4 1.0 v vcc = 3 v 10% 30 200 programmable pull down resistor pkl vcc = 2.2 v 10% 80 500 vcc = 3 v 10% 80 300 programmable pull up resistor pkh vcc = 2.2 v 10% 80 500 k w normal2 14 23 run 10 17 idle2 611 idle1 vcc = 3 v 10% fc = 13.5 mhz (typ. : vcc = 3.0 v) 1.1 2.8 ma normal2 8.0 12 run 4.5 9.5 idle2 2.5 6.5 idle1 vcc = 2.2 v 10 % fc = 10 mhz (typ. : vcc = 2.2 v) 0.5 1.5 ma slow 40 55 run 32 45 idle2 18 35 idle1 vcc = 3 v 10% fs = 32.768 khz (typ. : vcc = 3.0 v) 620 m a ta 50 c 10 ta 70 c 20 stop icc ta 85 c vcc = 2.0 to 3.6 v 0.2 50 m a note 1: typical values are for ta = 25 c and vcc = 5 v unless otherwise noted. note 2: i-dar is guaranteed for up to eight ports. note 3: i cc measurement condition (normal2): all functions are operational; output pins are open and input pins are fixed.
tmp91cu10 91cu10-184 4.3 ac characteristics (1) vcc = 2.5 to 3.6 v variable 12.5 mhz 16 mhz no. parameter symbol min max min max min max unit 1 osc. period (=x) t osc 62.5 31250 80 74 ns 2 clk width t clk 2x - 40 120 108 ns 3 a0 to a23 valid ? clk hold t ak 0.5x - 20 20 7 ns 4 clk valid ? a0 to a23 hold t ka 1.5x - 70 50 26 ns 5 a0 to a15 valid ? ale fall t al 0.5x - 15 25 30 ns 6 ale fall ? a0 to a15 hold t la 0.5x - 20 20 7 ns 7 ale high width t ll x - 40 40 24 ns 8 ale fall ? rd / wr fall t lc 0.5x - 25 15 10 ns 9 rd / wr rise ? ale rise t cl 0.5x - 20 20 7 ns 10 a0 to a15 valid ? rd / wr fall t acl x - 25 55 34 ns 11 a0 to a23 valid ? rd / wr fall t ach 1.5x - 50 70 61 ns 12 rd / wr rise ? a0 to a23 hold t ca 0.5x - 25 15 0 ns 13 a0 to a15 valid ? d0 to d15 input t adl 3.0x - 55 130 182 ns 14 a0 to a23 valid ? d0 to d15 input t adh 3.5x - 65 215 194 ns 15 rd fall ? d0 to d15 input t rd 2.0x - 60 100 103 ns 16 rd low pulse width t rr 2.0x - 40 120 108 ns 17 rd rise ? d0 to d15 hold t hr 000ns 18 rd rise ? a0 to a15 output t rae x - 15 65 54 ns 19 wr low pulse width t ww 2.0x - 40 120 108 ns 20 d0 to d15 valid ? wr rise t dw 2.0x - 55 105 68 ns 21 wr rise ? d0 to d15 hold t wd 0.5x - 15 25 5 ns 22 a0 to a23 valid ? wait input (1wait + n mode) t awh 3.5x - 90 190 199 ns 23 a0 to a15 valid ? wait input (1wait + n mode) t awl 3.0x - 80 160 162 ns 24 rd/wr fall ? wait hold (1wait + n mode) t cw 2.0x + 0 160 148 ns 25 a0 to a23 valid ? port input t aph 2.5x - 120 80 65 ns 26 a0 to a23 valid ? port hold t aph2 2.5x + 50 250 235 ns 27 wr rise ? port valid t cp 200 200 359 ns ac measuring conditions output level: high 2.2 v/low 0.8 v, cl=50 pf (however, cl = 100 pf for ad0 to ad15, a0 to a23, ale rd , wr , hwr , r/ w , clk ) input level: high 2.4 v/low 0.45 v (ad0 to ad15) high 0.8 vcc/low 0.2 vcc (except for ad0 to ad15)
tmp91cu10 91cu10-185 (2) vcc = 2.2 v 10 % variable 10 mhz no. parameter symbol min max min max unit 1 osc. period (=x) t osc 100 31250 100 ns 2 clk width t clk 2x - 40 160 ns 3 a0 to a23 valid ? clk hold t ak 0.5x - 30 20 ns 4 clk valid ? a0 to a23 hold t ka 1.5x - 80 70 ns 5 a0 to a15 valid ? ale fall t al 0.5x - 35 15 ns 6 ale fall ? a0 to a15 hold t la 0.5x - 35 15 ns 7 ale high width t ll x - 60 40 ns 8 ale fall ? rd / wr fall t lc 0.5x - 35 15 ns 9 rd / wr rise ? ale rise t cl 0.5x - 40 10 ns 10 a0 to a15 valid ? rd / wr fall t acl x - 50 50 ns 11 a0 to a23 valid ? rd / wr fall t ach 1.5x - 50 100 ns 12 rd / wr rise ? a0 to a23 hold t ca 0.5x - 40 10 ns 13 a0 to a15 valid ? d0 to d15 input t adl 3.0x - 110 190 ns 14 a0 to a23 valid ? d0 to d15 input t adh 3.5x - 125 225 ns 15 rd fall ? d0 to d15 input t rd 2.0x - 115 85 ns 16 rd low pulse width t rr 2.0x - 40 160 ns 17 rd rise ? d0 to d15 hold t hr 00ns 18 rd rise ? a0 to a15 output t rae x - 25 75 ns 19 wr low pulse width t ww 2.0x - 40 160 ns 20 d0 to d15 valid ? wr rise t dw 2.0x - 120 80 ns 21 wr rise ? d0 to d15 hold t wd 0.5x - 40 10 ns 22 a0 to a23 valid ? wait input (1wait + n mode) t awh 3.5x - 130 220 ns 23 a0 to a15 valid ? wait input (1wait + n mode) t awl 3.0x - 100 200 ns 24 rd / wr fall ? wait hold (1wait + n mode) t cw 2.0x + 0 200 ns 25 a0 to a23 valid ? port input t aph 2.5x - 120 130 ns 26 a0 to a23 valid ? port hold t aph2 2.5x + 50 200 ns 27 wr rise ? port valid t cp 200 200 ns ac measuring conditions output level: high 0.7 vcc/low 0.3 v vcc , cl = 50 pf input level: high 0.9 vcc/low 0.1 v vcc
tmp91cu10 91cu10-186 (3) read cycle a0 to a23 cl k x1 t osc t clk t ak a0 to ad15 t ll t al t la t adl t rd t lc t rr t acl t ach t adh d0 to d15 t cl t hr t rae t ca t aph2 t aph t awl t cw t awh t ka cs0 to 2 r/ w wait port input rd ad0 to ad15 ale
tmp91cu10 91cu10-187 (4) write cycle a0 to a23 cl k x1 a0 to a15 d0 to d15 cs0 to 2 r/ w wait port output wr , hwr ad0 to a15 ale t wd t ww t dw
tmp91cu10 91cu10-188 4.4 a/d conversion characteristics avcc = vcc, avss = vss parameter symbol min typ. max unit analog reference voltage (+) v refh vcc - 0.2 v vcc vcc analog reference voltage ( - ) v refl vss vss vss + 0.2 v analog input voltage range v ain v refl v refh v analog current for analog reference voltage vcc = 3 v 10% =1 0.5 1.5 ma vcc = 3 v 10% =0 i ref (v refl = 0 v) 0.02 5.0 m a error (not including quantizing errors) ? 1 3 lsb note 1: 1lsb = (v refh - v refl ) / 2 10 [v] note 2: the operation of the a/d converter is guaranteed only when fc (the high frequency oscillator) is used (it is not guaranteed when fs is used). it is guaranteed when f fph 3 4 mhz. note 3: the value icc includes the current which flows through the avcc pin. note 4: the operation of the tmp91cu10 is guaranteed within 2.7 to 3.6 v.
tmp91cu10 91cu10-189 4.5 serial channel timing (1) i/o interface mode ? sclk input mode variable 32.768 khz note ) 13.5 mhz unit parameter symbol min max min max min max sclk cycle t scy 16x 488 m s 1.18 m s output data ? rising edge or falling edge* of sclk t oss t scy /2 - 5x - 50 91.5 m s 172 ns sclk rising edge or falling edge * ? output data hold t ohs 5x - 100 152 m s 270 ns sclk rising edge or falling edge* ? input data hold t hsr 000ns sclk rising edge or falling edge* ? effective data input t srd t scy - 5x - 100 336 m s 714 ns note: system clock is fs, or input clock to prescaler is divisor clock of fs. *) the rising edge is used in sclk rising mode. the falling edge is used sclk falling mode. - sclk output mode variable 32.768 khz note ) 13.5 mhz unit parameter symbol min max min max min max sclk cycle (programmable) t scy 16x 8192x 488 m s 250 ms 1.18 655.4 m s output data ? sclk rising edge t oss t scy /2 - 5x - 50 427 m s 886 ns sclk rising edge ? output data hold t ohs 2x - 80 60 m s 68 ns sclk rising edge ? input data hold t hsr 000ns sclk rising edge ? effective data input t srd t scy - 2x - 150 428 m s 886 ns note: system clock is fs, or input clock to prescaler is divisor clock of fs. sclk input mode (sclk falling edge mode) output data txd input data rxd sclk sclk 3 3 2 2 1 1 0 0 valid valid valid valid t hsr t srd t ohs t oss t scy sclk output mode (only rising edge is used) o r sclk input mode (sclk falling
tmp91cu10 91cu10-190 4.6 event counter (ti0, ti4, ti8, ti9, tia,tib) variable 13.5 mhz parameter symbol min max min max unit clock cycle t vck 8x + 100 692 ns low level clock pulse width t vckl 4x + 40 336 ns high level clock pulse width t vckh 4x + 40 336 ns 4.7 interrupt and capture (1) nmi , int0 interrupts variable 13.5 mhz parameter symbol min max min max unit nmi , int0 to 4 low level pulse width t intal 4x 296 ns nmi , int0 high level pulse width t intah 4x 296 ns (2) int5 to 8 interrupts, capture the int4 to 7 input pulse width depends on the cpu operation clock and timer (9-bit prescaler). the following shows the pulse width for each clock. t intbl (int5 to 8 low level pulse width) t intbh (int5 to 8 high level pulse width) variable 13.5 mhz variable 13.5 mhz system clock selected prescaler clock selected min min min min unit 00 (f fph ) 8x + 100 692 8x + 100 692 ns 01 (fs) 8xt + 0.1 244.3 8xt + 0.1 244.3 0(fc) 10 (fc/16) 128x + 0.1 9.572 128x + 0.1 9.572 00 (f fph ) 1 (fs) (note 2) 01 (fs) 8xt + 0.1 244.3 8xt + 0.1 244.3 m s note 1: xt represents the frequency of the low frequency clock fs. calculated at fs = 32.768 khz. note 2: when using fs as the system clock, fc/16 cannot be selected as the prescaler clock. t sch t scl scout
tmp91cu10 91cu10-191 4.8 timing chart for bus request / bus acknowledge t cbah t baa t aba t brc t cbal t brc ( note2 ) ( note2 ) ( note1 ) clk ale busrq busak ad0 to ad15,a0 to a23, cs0 to cs2 ,r/ w rd , wr , hwr variable 13.5 mhz parameter symbol min max min max unit busrq busrq set - up time to clk t brc 120 120 ns clk ? busak busak falling edge t cbal 1.5x + 120 231 ns clk ? busak rising edge t cbah 0.5x + 40 77 ns output buffer off to busak t aba 080080ns busak to output buffer on t baa 080080ns note 1: even if the busrq signal goes low, the bus will not be released while the wait signal is low. the bus will only be released when busrq goes low while wait is high. note 2: this line shows only that the output buffer is in the off state.it does not indicate that the signal level is fixed. just after the bus is released, the signal level set before the bus was released is maintained dynamically by the external capacitance. therefore, to fix the signal level using an external resistor during bus release, careful design is necessary as fixing of the level is delayed. the internal programmable pull-up/pull-down resistor is switched between the active and non- active states by the internal signal.

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